Integrated circuit memory devices are often organized into rows and columns of memory cells, with the rows and columns separately selected based on the value of the portions of the memory address which represent row and column addresses. In such devices, the term "word lines" generally refers to a set of conductors of which one, when active, selects the addressed row of memory cells; the term "bit lines" generally refers to a set of conductors which communicate data between memory cells in the addressed row and a sense amplifier. The sense amplifier is a circuit which senses the data state of the data on an associated bit line, and which generally amplifies the sensed data state for communication to output stages of the circuit.
Due to the drive capability of static memory cells, where the memory cell consists of a latch, multiple columns in many static random access memories (SRAMs) share a single sense amplifier. With reference to FIG. 1, each column of a memory array is connected by line 3 to its associated sense amplifier 10 through each column's associated pass transistor 7. Pass transistor 7, when turned on, allows electrical connection of a selected column to sense amplifier 10. Since the change in charge, Q, is equal to the capacitance, C, times the change in voltage, V, across the capacitor in pass transistor 7, that is Q=C V, then the time, t, to charge the capacitor is a function of Q over the charging current, I, or rather t=f(Q/I). It is apparent that pass transistor 7 should be as large as possible in order to drive sense amp 10. However, as pass transistor 7 increases in size, its capacitance increases in size thereby decreasing the switching speed of the pass transistor and thus slowing down the operation of the memory device.